Andrew Ang

Sydney

Andrew Ang in Sydney works at Arista Networks (FPGA Design Engineer) and was educated at Victoria University of Wellington.

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Jobs

Arista Networks Jan 2019 - Present
FPGA Design Engineer

Dosec Design Apr 2018 - Jan 2019
Junior Hardware Design Engineer

Victoria University of Wellington Mar 2017 - Mar 2018
Masters Student

Education

Victoria University of Wellington
Master of Engineering - MEng. Distinction

Victoria University of Wellington 2013 - 2016
Bachelor’s Degree. Electrical and Electronics Engineering

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